1. Field of the Invention
The present invention generally relates to non-volatile semiconductor memory devices of an electrically erasable type. More particularly, the present invention is concerned with a non-volatile semiconductor memory device of a batch erase type such as a flash memory device in which data stored in a plurality of memory cells can be electrically erased at one time. More specifically, the present invention relates to improvements in a circuit configuration directed to erasing data stored in memory cells at one time.
The flash memory is an electrically programmable and erasable device and can be relatively easily implemented by using the integrated circuit technology. Further, the flash memory is of non-volatile type. From these viewpoints, the flash memory is attractive and is used in various applications such as an external storage device and a portable telephone set.
2. Description of the Related Art
FIG. 1A is a cross-sectional view of a cell of a flash memory device, and FIG. 1B shows an operation thereof. Referring to FIG. 1A, a P-type semiconductor substrate 1 has N.sup.+ -type impurity diffused regions 2 and 3, which function as a drain and a source of the cell transistor, respectively. A channel can be formed between the drain 2 and the source 3. An insulating film (not shown) is formed on the channel. A floating gate FG is formed on the insulating film. An insulating film is formed on the floating gate FG, and a control gate CG is formed on the insulating film. In FIGS. 1A and 1B, symbols Vd, Vs and Vg respectively denote a drain voltage, a source voltage and a gate voltage.
Data can be written into the memory cell as follows. The drain voltage Vd is set to a first voltage Vp. The voltages Vd and Vp are equal to or lower than, for example, 6V (Vd=Vp=.about.6V). The gate voltage Vg is set to a second voltage Vpp, which is higher than the voltage Vp (&gt;Vp). Further, the source voltage Vs is set to 0V, which is the reference potential with respect to the voltages. Hence, as indicated by *1 in FIG. 1A, electrons are injected in the floating gate FG from the drain.
Data can be erased as follows. The source voltage Vs is set to a third voltage Vcc, which is lower than the first voltage Vp and is equal to or lower than, for example, 5V. The gate voltage Vg is set to a negative voltage which is lower than 0V, and the drain is set to an open state. Hence, as indicated by *2, the electrons are drawn to the source from the floating gate FG.
Data can be read as follows. The gate voltage Vg is set to the third voltage Vcc, and the drain voltage Vd is set to a voltage equal to or lower than 1V (Vd=.about.1V). In this case, it is determined whether a current flows in the drain. In other words, it is determined whether the data stored in the cell is "1" or "0". The second voltage Vpp is called a write/erase voltage, and the third voltage Vcc is a read voltage.
Generally, the erase operation of the flash memory is not carried out on the cell basis but a group of cells (for example, every 64 Kbytes) are erased at one time. Such a group is called "sector". Current control circuits are provided to respective sectors. Data is erased by causing the source current to flow in the cell. In this point of view, the current control circuits are also called source current control circuits.
FIG. 2 is a block diagram of a configuration of the flash memory which employs the sector-basis erasing operation. The flash memory shown in FIG. 2 includes a plurality of sectors 10.sub.1 through 10.sub.n where n is an integer. The sectors 10.sub.1 through 10.sub.n respectively include cell arrays 14.sub.1 through 14.sub.n and source current control circuits 12.sub.1 through 12.sub.n. The source current control circuits 12.sub.1 through 12.sub.n are connected, via a wiring line 16, to a current source to which a power supply generating the third (power supply) voltage Vcc is connected. Symbols R1 through Rn denote wiring resistances of portions between the adjacent sectors.
FIG. 3 is a circuit diagram of the source current control circuit 12.sub.1. Each of the other source current control circuits 12.sub.2 through 12.sub.n has the same configuration as shown in FIG. 3. The source current control circuit 12.sub.1 includes P-channel field effect transistors (for example, MOS transistors) MP1 and MP2, and N-channel field effect transistors (for example, MOS transistors) MN1 and MN2. An erase signal ER1 for the sector 10.sub.1 is applied to the gates of the transistors MP1 and MN1, which are set to a high level during the erasing operation. The current source shown in FIG. 2 is connected to the source of the transistor MP2. The drains of the transistors MP2 and MN2 are connected together and are further connected to the cell array 14.sub.1.
When data stored in the cell array 14.sub.1 are erased at one time in the batch formation, the erase signal ER for the sector 10.sub.1 is set to the high level. Hence, the transistor MN1 is turned ON, and the transistor MP2 is turned ON. Hence, as indicated by the thick solid line, a current I1 is supplied to the cell array 14.sub.1 from the current source via the transistor MP2.
However, the above prior art has the following disadvantages.
As has been described previously, the wiring line 16 have the wiring resistances R1 through Rn. Since the source current control circuits 12.sub.1 through 12.sub.n have the same circuit configuration, the source currents I1 through In flowing in the cell arrays 14.sub.1 through 14.sub.n have different values which depend on the wiring resistances R1 through Rn. That is, the selector 10.sub.1 is connected to the current source via the resistance R1, so that the largest source current I1 flows in the cell array 14.sub.1. In contrary, the selector 10.sub.n is connected to the current source via the resistances R1 through Rn, so that the smallest source current In flows in the cell array 14.sub.n. That is, as shown in FIG. 4, the source currents I1, I2, I3, . . . , In have decreased values in that order. FIG. 4 shows Vs-Is (source voltage vs source current) characteristics of the source current control circuits 12.sub.1, 12.sub.2 and 12.sub.3, in which the horizontal axis denotes the source voltage Vs and the vertical axis denotes the source current Is.
Since the source currents Is of the sectors 10.sub.1 through 10.sub.n have different values, different magnitudes of stress are applied to the memory cells of the memory cell arrays 14.sub.1 through 14.sub.n. The above fact causes the following problems. For example, even if the source current I1 has an amount which certainly ensures the erasing operation on the cell array 14.sub.1, the source current In may be insufficient to certainly ensure the erasing operation on the cell array 14.sub.n during the same erasing time as that for the cell array 14.sub.1. If the source current In has an amount which certainly ensures the erasing operation on the cell array 14.sub.n, the source current I1 may excessively erase data stored in the cells of the cell array 14.sub.1 during the same erasing time as that for the cell array 14.sub.n. If the cells are excessively subjected to the erasing operation, the electrons stored in the floating gate FG are reduced. It can be seen from the above that it is necessary to change the erasing time in accordance with the amount of the source current in order to eliminate the above problems.
However, if a plurality of sectors are simultaneously subjected to the erasing operation, the above problems cannot be eliminated. For example, a plurality of sectors are subjected to the simultaneous erasing operation in a test carried out before shipping in order to reduce the test time. Even if the source currents are supplied to the sectors during the same time, the source currents supplied to the different sectors have different amounts, so that the sectors have different erased states.
If a common erasing time is defined as the erasing time necessary to obtain a desired erased state by the source current which has the smallest amount among the source currents supplied to the sectors subjected to the simultaneous erasing operation, some sectors supplied with comparatively large amounts of source currents will be excessively erased. In contact, if the common erasing time is defined as the erasing time necessary to obtain the desired erased state by the source current which has the smallest amount among the source currents supplied to the sectors subjected to the simultaneous erasing operation, some sectors supplied with comparatively small amounts of source currents will be insufficiently erased. Hence, the reliability of the flash memory will be degraded.